SGS DATABOOK ndash Z MICROPROCESSOR FAMILY ndash TH Edition for sale in Manassas, VA
Local pick-up preferred (please call first) but will ship at the buyer s expense. Kingston Books IMG_Illustrated Charts Graphs Tables Logic Functions Pin Configurations Z CPU Block Diagram Z CPU Registers Interrupts General Operation Interrupt Priority Z Instruction Set and Bit Load Group Exchange Block Transfer Block Search Groups -Bit Arithmetic and Logical Group Rotate and Shift Group Bit Set Reset and Test Group Jump Group Call and Return Group input and Output Group Summary of Flag Operations Symbolic Notation Pin Descriptions CPU Timing Memory Read and Write Cycles Interrupt Request Acknowledge Cycle Non-Maskable Interrupt Request Cycle Bus Request Acknowledge Cycle Halt Acknowledge Cycle Reset Cycle AC Characteristics Absolute Maximum Ratings Standard Test Conditions DC Characteristics Capacitance Package Dimensions (in mm) CPU Registers Interrupt Enable Disable Operation. Z FAMILYThe design philosophy or all Z Family members is to help engineers design microcomputer systems with fewer compnts that have more functions per chip. The Z CPU offers many more features and functions than its competitors. The Z Z CPU Central Processing Unit has rapidly established itself as the most sophisticated most powerful. And most versatile -bit microprocessor in the world. In addition to being source-code compatible with the A ( vs. ) and numerous other features that simplify hardware requirements and reduce programming effort while increasing throughput. The dual-register set of the Z CPU allows high-speed con switching and more efficient interrupt processing. Two index registers give additional memory-addressing flexibility and simplify the task of programming. Interfacing to dynamic memory is simplified by on-chip programmable refresh logic. Block moves plus string-and bit-manipulation instructions reduce programming effort program size and execution time. The traditional functions of a microcomputer system (parallel I O serial I O counting timing and direct memory access) are easily implemented by the Z CPU and the following well-proven family of Z peripheral devices Z PIO Z SIO Z DART Z CTC and Z DMA. The easily programmed dual channel Z Z PIO Parallel Input Output Controller offers -bit I O ports with individual handshake and pattern recognition logic. Both I O ports operate in either byte or a bit mode. In addition this device can be programmed to generate interrupts for various status conditions. Conts by Chapter Z CPU.-Z L CPU.-Z DMA.-Z PIO.-Z CTC.-Z SIO.-Z SIO.-Z DART.-M.-Paperback pages Photos and contact info on Advertigo website.
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